The present invention relates to an address decoder for replacing defective memory cells with redundant (auxiliary) memory cells, which may be used in various types of semiconductor memory devices.
As the memory capacity of a semiconductor memory device increases, the production yield in its manufacture tends to decline due to defective memory cells. To deal with this problem, redundant memory cells are provided in the semiconductor memory device, to improve the yield by replacing defective memory cells with the redundant memory cells. The replacement is performed in units of rows or columns in the memory cell array.
FIG. 5 shows a circuit related to the row address decoder which is provided with a function to replace defective memory cells in units of rows. For the sake of simplification, in the circuit in FIG. 5, the addresses are assigned five bits, A4 to A0 and 2 redundant word lines RWL0 and RWL1 are provided for the 32 word lines WL0 to WL31 which are obtained by decoding the addresses.
The addresses A4 to A0 are supplied to the pre-decoder 2 via the address buffer 1 and, for instance, the two bits A2 and A1 are decoded in the pre-decoder 2 to become B0 to B3 and the addresses A4, A3 and A0 and B0 to B3, which are addresses A2 and A1 when decoded, are supplied to the main decoder 3 to be fully decoded. Then, one of the word lines WL0 to WL31 is selected and is set to high. The word line WL0, for example, may be selected in the following manner using the nMOS transistor 30 for drive and the decoders 31 and 32: When the output of the decoder 32 is set to high (potential VCC) and, at the same time, the output of the decoder 31 is set to high (potential VCC+.alpha.) the nMOS transistor 30 is turned ON to set the word line WL0 to high.
If defective memory cells are detected in pre-shipment tests of the semiconductor memory device, the following information on the redundant addresses is written in the redundant address memory unit 4, with the row address that includes the defective memory cell assigned as RA. In other words, the low order three bits of the RA and the redundancy selection signals S0, S1 are written at the addresses indicated with the two high-order bits of the RA in the redundant address memory unit 4. The redundancy selection signal S0 is the select/not select =`1`/`0` of the redundant word line RWL0 and the redundancy selection signal S1 is the select/not select =`1`/`0` of the redundant word line RWL1. This write is performed, for instance, by melting a fuse electrically.
The aforementioned three bits of the RA that are thus output from the redundant address memory unit 4 are supplied to one set of the input terminals of the comparator circuit 5 and to the other set of input terminals of the comparator circuit 5, the low order three bits of the address from the address buffer 1 are supplied. If these three-bit sets match, the comparator circuit 5 sets the match signal EQ to high. The match signal EQ is supplied to the decoder 31 which is a component within the main decoder 3 and all the other circuits that are similar to it. When the match signal EQ is at high, the output from the decoder 31 and the outputs from all the other similar circuits in the main decoder 3 are at the ground potential VSS.
The redundant decoder 6 is provided with two sets of components, one of which consists of the nMOS transistor 60 which is identical to the nMOS transistor 30 in the main decoder 3, the decoder 61 and the gate driver 62, which are similar to the decoders 31 and 32 in the main decoder 3. The other set consists of the nMOS transistor 63, the decoder 64 and the gate driver 65. The only difference between the gate drivers 62 and the decoder 32 is that the decoder 32 has a decoding circuit added to the back stage of the gate driver.
The match signal EQ is also supplied to the gate drivers 62 and 65. The redundancy selection signals S0 and S1 are supplied to the decoders 61 and 64 respectively. The output of the decoder 61 is set to high (VCC+.alpha.) when the match signal EQ is at `1` and the redundancy selection signal S0 is at `1`. The output of the decoder 64 is set to high (VCC+.alpha.) when the match signal EQ is at `1` and the redundancy selection signal S1 is at `1`. The outputs of the gate drivers 62 and 65 are set to high (VCC) when the match signal EQ is at `1`.
With this structure, when there is a defect in the first line of the memory cell, for example, the redundant word line RWL0 is selected to replace the word line WL0. The word line WL0 is set to the ground potential VSS and the redundant word line RWL0 is set to the potential. VCC+.alpha..
The number of stages in the logic gates between the input and the output of the main decoder 3, the number of stages in the logic gates between the input and the output of the comparator circuit 5 and the number of stages in the logic gates between the input and the output of the redundant decoder 6 is relatively large, for example, at 12, 4 and 8 respectively, as shown in FIGS. 2 and 3. While the difference in the number of stages of logic gates in the decoder 31 and the decoder 32 is 8, the difference in the number of stages between the decoder 61 and the gate driver 62 is relatively low, i.e., 3.
Now, in order to ensure sufficient drive capacity for the nMOS transistor that drives the word lines, for example, the nMOS transistor 60, the gate of the nMOS transistor 60 must be fully charged with the power-supply potential. However, since the nMOS transistor 622 in FIG. 3, for example that is connected to this gate, operates at approximately the threshold potential when its source nears the power-supply voltage VCC, the ON resistance is increased and it takes a considerable length of time to charge the gate of the nMOS transistor 60. Because of this, the double boost wiring GL1 that connects the output terminal of the gate driver 62 with the gate of the nMOS transistor 60 is increased comparatively gently as shown in FIG. 4A.
Thus, when the clock frequency is raised in order to access the semiconductor memory device at high speed, the output potential of tile decoder 61 rises before the potential of the double boost wiring GL1 has risen sufficiently. As a result, the speed at which the potential of the redundant word line RWL0 rises to the vicinity of the VCC+.alpha. is reduced. This delays access to the memory cell. Even if the pre-charge time for the redundant word line RWL0 is lengthened to ensure that the potential of the redundant word line RWL0 will rise sufficiently, the access is delayed for that amount of time.